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MC44824/25
PLL Tuning Circuits with I2C Bus
The MC44824/25 are tuning circuits for TV and VCR tuner applications. They contain on one chip all the functions required for PLL control of a VCO. The integrated circuits also contain a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44824/25 are manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
TV AND VCR PLL TUNING CIRCUITS WITH 1.3 GHz PRESCALER AND I2C BUS
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* * * * * * * * * * *
Complete Single Chip System for MPU Control (I2C Bus). Data and Clock Inputs are 3-Wire Bus Compatible Divide-by-8 Prescaler Accepts Frequencies up to 1.3 GHz 15 Bit Programmable Divider Reference Divider: Programmable for Division Ratios 512 and 1024 3-State Phase/Frequency Comparator 4 Programmable Chip Addresses 3 Output Buffers (MC44824) respectively 5 Output Buffers (MC44825) for 10 mA/15 V Operational Amplifier for use with External NPN Transistor SO-14 Package for MC44824 and SO-16 for MC44825 High Sensitivity Preamplifier Fully ESD Protected
D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14)
16 1
D SUFFIX PLASTIC PACKAGE CASE 751B (SO-16)
PIN CONNECTIONS
MC44824
MOSAIC is a trademark of Motorola, Inc.
PD XTAL1 XTAL2 SDA SCL B7 CA
1 2 3 4 5 6 7 (Top View) MC44825
14 UD 13 GND 12 HF2 11 HF1 10 V CC 9 B1 8 B2
PD XTAL1 XTAL2 SDA Package SO-14 TA = - 20 to + 80C SO-16 SCL B7 B4 CA
1 2 3 4 5 6 7 8 (Top View)
16 UD 15 GND 14 HF2 13 HF1 12 VCC 11 B 0 10 B1 9 B2
ORDERING INFORMATION
Device MC44824D MC44825D Operating Temperature Range
(c) Motorola, Inc. 1996
Rev 1
MOTOROLA ANALOG IC DEVICE DATA
1
MC44824/25
Representative Block Diagram
VCC 5.0 V 10 (12) 6 (6) B7 (7) B4 8 (9) B2 Buffers Latches T8 T13 P-On Reset DTB2 POR CA SDA SCL 7 (8) 4 (4) 5 (5) I2C Bus Receiver CL Data RL DTF 4 Shift Register 15 Bit 7 9 (10) B1 (11) B0
UD 14 (16) 1 (1) 2.7 V Operational Amplifier T9, T12, T14 T10, T11 Latches Fout Fref Phase Comp PD
Fout Fref 13 (15) Test Logic DTB1 Gnd
512/1024
Ref Divider 2 (2) 3.2 or 4.0 MHz Osc 3 (3)
Latches A
XTAL1 XTAL2
Latches B
TDI
Gnd
11 (13) HF Input1 12 (14) HF Input2
Preamp /8 Prescaler Program Divider 15 Bit Fout Latch Control
DTS, EN MC44825 Pin Numbers ( ) This device contains 3,204 active transistors.
PIN FUNCTION DESCRIPTION
Pin MC44824 1 2 3 4 5 6, 8, 9 - 7 10 11, 12 13 14 MC44825 1 2 3 4 5 - 6, 7, 9, 10, 11 8 12 13, 14 15 16 PD XTAL1 XTAL2 SDA SCL B7, B2, B1 B7, B4, B2, B1, B0 CA VCC HF1/HF2 GND UD Symbol S bl Input of tuning voltage amplifier First crystal input is the active pin at the oscillators Second crystal input is the internal ground Data input Clock input of the I2C bus Band buffer (open collector) outputs for up to 10 mA Band buffer (open collector) outputs for up to 10 mA Chip address selection pin Supply voltage, typical 5.0 V Symmetric HF inputs from local oscillator Ground Output of the tuning voltage amplifier. Needs an external NPN with pull-up resistor to drive the varicaps Description D ii
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MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Pin Rating Ri Power Supply Voltage (VCC) Band Buffer "Off" Voltage Band Buffer "On" Current Storage Temperature Operating Temperature Range RF Input Level (10 MHz to 1.3 GHz) MC44824 10 6, 8, 9 6, 8, 9 - - 11, 12 MC44825 12 6, 7, 9, 10, 11 6, 7, 9, 10, 11 - - 13, 14 Value Vl 6.0 15 15 - 65 to +150 - 20 to +80 1.5 Unit Ui V V mA C C Vrms
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C, unless otherwise noted.)
Pin Characteristic Ch ii VCC Supply Voltage Range VCC Supply Current (VCC = 5.0 V) Band Buffer Leakage Current when "Off" at 12 V Band Buffer Saturation Voltage when "On" at 10 mA Data Saturation Voltage at 15 mA Acknowledge "On" Data/Clock/Enable Current at 0 V Data/Clock/Enable Current at 5.0 V Data/Clock/Enable Input Voltage Low Data/Clock/Enable Input Voltage High Clock Frequency Range Oscillator Frequency Range Operational Amplifier Input Current Phase Detector Current in High Impedance State Charge Pump Current of Phase Comparator, T14 = 0 Charge Pump Current of Phase Comparator, T14 = 1 HF CHARACTERISTICS (See Figure NO TAG) Pin Characteristic Ch ii DC Bias Input Voltage Range 80-150 MHz 150-600 MHz 600-950 MHz 950-1300 MHz MC44824 11, 12 11, 12 11, 12 11, 12 11, 12 MC44825 13, 14 13, 14 13, 14 13, 14 13, 14 Min Mi - 10 5.0 10 50 Typ T 1.6 - - - - Max M - 315 315 315 315 Unit Ui V mVrms MC44824 10 10 6, 8, 9 6, 8, 9 4 4, 5 4, 5 4, 5 4, 5 5 2, 3 1 1 1 1 MC44825 12 12 6, 7, 9, 10, 11 6, 7, 9, 10, 11 4 4, 5 4, 5 4, 5 4, 5 5 2, 3 1 1 1 1 Min Mi 4.5 - - - - -10 0 - 3.0 - 3.15 -15 -15 30 100 Typ T 5.0 40 0.01 1.6 - - - - - - 3.2 0 0 40 125 Max M 5.5 55 1.0 1.8 1.0 0 1.0 1.5 - 100 4.05 15 15 60 200 Unit Ui V mA A V V A A V V kHz MHz nA nA A A
MOTOROLA ANALOG IC DEVICE DATA
3
MC44824/25
Figure 1. HF Sensitivity Test Circuit
I2C Bus Bus Controller
HF Generator HF Out Gnd 50 Cable 470 50 470 VCC 1.0 nF In
Device is in test mode. B2 and B7 are "On". Sensitivity is level of HF generator on 50 load.
1 1.0 GHz
Data Format and Bus Receiver The circuit receives the information for tuning and control via the I2C bus. The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA CA CA CA CO FM CO BA FL BA STO STO FM FL
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CCCCCCCCCCCC CCCCCCCCCCCC
VCC 5.0 V SDA, SCL VCC HF 1.0 nF HF Gnd -j 0 +j 0.5 0.5 ZO = 50 1.3 GHz 1 2 2 500 MHz 50 MHz
MC44824/25 B7 B2 Frequency Counter
Figure 2. Typical HF Input Impedance
0.5
1
2
STO
4_STA CA FM FL CO BA STO STA = Start Condition STO = Stop Condition CA = Chip Address Byte CO = Data Byte for Control Information BA = Band Information FM = Data Byte for Frequency Information (MSB's) FL = Data Byte for Frequency Information (LSB's)
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 3. Complete Data Transfer Process
SDA
SCL 1-7 S STA ADDRESS CA R/W ACK DATA ACK DATA ACK 8 9 1-7 8 9 1-7 8 9 P STO
Figure 4 shows the five bytes of information that are needed for circuit operation: there is the chip address, two bytes of control and band information and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received, the third data byte is ignored. If five or more data bytes are received, the fifth and following data bytes are ignored and the last acknowledge pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. Frequency information is preceded by a Logic "0". If the function bit is Logic "1" the two following bytes contain control and band information. The first data byte, shifted after the chip address, may be byte CO or byte FM. The two permissible bus protocols with five bytes are shown in Figure 4.
Figure 4. Definition of Bytes
CO_Information BA_Band Information
FM_Frequency Information FL_Frequency Information CA_Chip Address
FM_Frequency Information FL_Frequency Information
CO_Information BA_Band Information
* B0 and B4 are only available on MC44825. On MC44824 this data is random.
Chip Address The chip address is programmable by Pin 7 (8), CA.
CA - Pin 7 (8) Gnd to 0.1 VCC1 Open or 0.2 VCC1 to 0.3 VCC1 0.4 VCC1 to 0.7 VCC1 0.8 VCC1 to 1.1 VCC1 Address (HEX.) C0 C2 C4 C6
Bits B0, B1, B2, B4, B7: Control the Band Buffers
B0, B1, B2, B4, B7 = 0 B0, B1, B2, B4, B7 = 1 Buffer "Off" Buffer "On"
MOTOROLA ANALOG IC DEVICE DATA
EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE
1 T14 X T13 X T12 B4* T11 X T10 B2 T9 T8 ACK ACK B7 B1 B0* 0 N14 N6 1 N13 N5 0 N12 N4 0 N11 N3 0 N10 N2 N9 N1 N8 N0 0 ACK ACK ACK N7 1 0/1 0/1
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEE
0 N14 N6 N13 N5 N12 N4 N11 N3 N10 N2 N9 N1 N8 N0 ACK ACK N7 1 T14 X T13 X T12 B4* T11 X T10 B2 T9 T8 ACK ACK B7 B1 B0*
Bit T8: Controls the Output of the Operational Amplifier
T8 = 0 T8 = 1 Normal Operation Operational Amplifier Active Output State of Operational Amplifier Switched "Off", Output Pulls High Through an External Pull-Up Resistor
Bits T9, T12: Control the Phase Comparator
T9 1 1 0 0 T12 0 1 0 1 Function Normal Operation High Impedance Upper Source "On" Only Lower Source "On" Only
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MC44824/25
Bits T10, T11: Control the Reference Ratio
T10 0 0 1 1 T11 0 1 0 1 512 1024 1024 512 Division Ratio
Bit T13: Switches the Internal Signals Fref and FBY2 to Bit T13: the Band Buffer Outputs (Test)
T13 = 0 T13 = 1 Normal Operation Test Mode Fref Output at B7 FBY2 Output at B2
Bits B2 and B7 have to be "Off", B2 = B7 = 0 in the test mode. Fref is the reference frequency. FBY2 is the output frequency of the programmable divider, divided by two.
The division ratio definition is given by: N = 16384 x N14 + 8192 x N13 + ... + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 17 Where N0 ... N14 are the different bits for frequency information. The counter may be used for any ratio between 17 and 32767 and reloads correctly as long as its output frequency does not exceed 1.0 MHz. The data transfer between latches A and B (signal TDI) is also initiated by any start condition on the I2C bus. At power-on, the whole bus receiver is reset and the programmable divider is set to a counting ration of N = 256 or higher. The first I2C message must be sent only when the POWER ON RESET is completed. The Prescaler The prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is phase and frequency sensitive and has very low output leakage current in the high impedance state. The Tuning Voltage Amplifier The amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The tuning voltage amplifier needs an external NPN with a pull-up resistor to generate the tuning voltage. The amplifier can be switched "Off" through bit T8. When bit T8 is "One", the amplifier is "Off". The tuning voltage is then pulled high by the external pull-up resistor. Figure 5 shows a possible filter arrangement. The component values depend very much on the application (tuner characteristic, reference frequency, etc.). As a starting point for optimization, the component values in Figure 5 may be used for 7.8125 kHz reference frequency in a multiband TV tuner. The Oscillator The oscillator uses a 4.0 MHz crystal tied to ground "or between Pins 2 and 3" through a series capacitor. The crystal oscillates in its series resonance mode. The voltage at Pin 13 XTAL1, has low amplitude and low harmonic distortion. Pin XTAL2 is the internal ground of the oscillator; it is connected internally to ground Pin 13 (15).
Bit T14: Controls the Charge Pump Current of the Bit T14: Phase Comparator
T14 = 0 T13 = 1 Pump Current 40 A Typical Pump Current 125 A Typical
The Band Buffers BA_Band Information MC44824 14 Pin version
B7 X X X X B2 B1 X ACK
MC44825 16 Pin version
B7 X X B4 X B2 B1 B0 ACK
The band buffers are open collector buffers and are active "low" at Bn = 1. They are designed for 10 mA with a typical "On" resistance of 160 . These buffers are designed to withstand relative high output voltage in the "Off" state. B2 and B7 buffers may also be used to output internal IC signals (reference frequency and programmable divider output frequency divided by 2) for test purposes. The bit B2 and/or B7 have to be zero if the buffers are used for these additional functions. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider, this double latch scheme is needed to assure correct data transfer to the counter.
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MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 5. Typical Tuner Applications
UHF VHF B III 6 5.0 V 10 Mixer B. P. Filter 1.0 nF 12 11 B7 8 B2 9 B1 Bus Rec Program Divider 5 4 7 Osc & 2 Ref Div Phase Comp SCL SDA CA
IF
Antenna Filter
MC44824
/8 Pres
Fosc 1.0 nF Oscillator Gnd 13 16 33 V AGC VTUN 22 k 330 p (See Note) 47 nF 22 nF 47 k 2.7 V 1 3
12 pF 3.2/4.0 MHz
UHF VHF B III 7 5.0 V 12 Mixer B. P. Filter 1.0 nF 14 13 B4 9 B2 10 B1 11 B0 Bus Rec
External Switching
IF
6 B7 5 4 8 Osc & 2 Ref Div Phase Comp SCL SDA CA
Antenna Filter
MC44825
/8 Pres
Program Divider
Fosc 1.0 nF Oscillator Gnd 15 16 33 V AGC VTUN 22 k 330 p (See Note) 47 nF 22 nF 47 k 2.7 V 1 3
12 pF 3.2/4.0 MHz
NOTE:
C2 = 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
7
MC44824/25
OUTLINE DIMENSIONS
D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
D SUFFIX PLASTIC PACKAGE CASE 751B-05 (SO-16) ISSUE J
9
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G K C -T-
SEATING PLANE
R
X 45 _
F
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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*MC44824/D*
MOTOROLA ANALOG IC DEVICE DATA MC44824/D

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